Keynote: Pr. Lionel Torres

“Normally-off“ computing for Smart systems

Pr. Lionel Torres Bio

Lionel Torres obtained respectively my Master and PhD degree in 1993 and 1996 from the University of Montpellier. From 1996 to 1997 I was in ATMEL company as IP core methodology R&D engineer. From 1997 to 2004 he was assistant professor at the University of Montpellier, Polytech'Montpellier (Microelectronic design) and LIRMM laboratory. Since 2004, he is full Professor and was at the head of the Microelectronic department of the LIRMM from 2007 to 2010. I am now deputy head of Polytech'Montpellier (engineering school of Montpellier) in charge of research, industrial and international relationship. He is at the Head of the Labex NUMEV (Laboratory of Excellence on digital hardware solutions, Environmental and Organic Life Modeling). His research interests and skills concern system level architecture, with a specific focus on Non-Volatile Computing based on emerging technologies, especially MRAM. He leads several European, national and industrial projects in this field. He is involved in different major conference as DATE, VLSI, FPL, ISVLSI, DAC and is (co)author of more than 40 journal papers and 150 conference publications and 7 patents.


The scaling limits of CMOS have pushed many researchers to explore alternative technologies for beyond CMOS circuits. In addition to the increased device variability and process complexity led by the continuous decreasing size of CMOS transistors, heat dissipation effects limit the density and speed of current systems-on-chip. For beyond CMOS systems, the emerging memory technology STT-MRAM is seen as a promising alternative solution. This talk shows first how STT- MRAM can improve energy efficiency and reliability of future systems (HPC & Embedded Systems). We will present the potential of STT-MRAM to design non-volatile processor with two interesting capabilities for energy-efficient and reliable embedded systems: instant-on/off and rollback. We will also discuss about a hybrid design exploration flow to investigate the overall performance impact of using STT-MRAM into the memory hierarchy of HPC systems.